Computer-Aided Verification: 2nd International Conference, CAV '91 New Brunswick, NJ, June 18-21, 1990 Proceedings

From Book News, Inc.
Four articles reprinted from a special issue of Formal Methods in System Design v.1, nos.2-3, discuss the formal verification of computer hardware. They survey the various methods, offer a generic format for a graphical presentation, and describe techniques for reducing the computational cost. No index. Annotation copyright Book News, Inc. Portland, Or.

Book Description
This volume contains the proceedings of the second workshop on Computer Aided Verification, held at DIMACS, Rutgers University, June 18-21, 1990. It features theoretical results that lead to new or more powerful verification methods. Among these are advances in the use of binary decision diagrams, dense time, reductions based upon partial order representations and proof-checking in controller verification. The motivation for holding a workshop on computer aided verification was to bring together work on effective algorithms or methodologies for formal verification - as distinguished, say, from attributes of logics or formal languages. The considerable interest generated by the first workshop, held in Grenoble, June 1989 (see LNCS 407), prompted this second meeting. The general focus of this volume is on the problem of making formal verification feasible for various models of computation. Specific emphasis is on models associated with distributed programs, protocols, and digital circuits. The general test of algorithm feasibility is to embed it into a verification tool, and exercise that tool on realistic examples: the workshop included sessions for the demonstration of new verification tools.


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